D-Wave unveils gate-model fault-tolerant roadmap targeting 100 logical qubits by 2032
D-Wave Quantum Inc. (NYSE: QBTS) published on 2026-06-01 a gate-model development roadmap, disclosed via an 8-K (Items 7.01 and 9.01), outlining a staged path to a 100-logical-qubit fault-tolerant superconducting system by 2032. Per D-Wave's release, milestones are: a 17-physical-qubit system in 2026 with logical error rates about 2x lower than physical; a 49-physical-qubit system in 2027 (~20x error reduction); a 181-physical-qubit system in 2028 (~2,000x error reduction); a 10-logical-qubit system supporting first fault-tolerant algorithms in 2030; and a 100-logical-qubit system capable of more than one million operations in 2032. The architecture centers on dual-rail superconducting qubits with embedded error detection (~90% of errors), which D-Wave states targets a per-cycle error-reduction factor (Lambda) of about 10. This event was surfaced on 2026-06-02 after the scheduled 2026-06-01 run had completed.
D-Wave, historically focused on quantum annealing, is committing to a gate-model superconducting program with a concrete 2026 near-term deliverable (a 17-qubit dual-rail system with logical error below physical), a strategic-direction expansion that diversifies its modality exposure; the headline 2030-2032 targets remain forward-looking and unverified.
If the 2026 dual-rail milestone is demonstrated and independently benchmarked, it would mark D-Wave's credible entry into the gate-model race alongside IBM, Google, and IonQ; absent demonstrated results, the roadmap is an aspirational positioning statement.