imec presents a world-first functioning silicon quantum-dot qubit device fabricated with High-NA EUV lithography on a 300mm CMOS line, with 6nm plunger-and-barrier-gate gaps targeting million-qubit scale-up
On 2026-05-19 at the ITF World 2026 conference in Antwerp, imec (Interuniversity Microelectronics Centre, Leuven) presented what it described as a world-first integrated hardware device consisting of a functioning network of silicon quantum-dot spin qubits fabricated using High-NA Extreme Ultraviolet (EUV) lithography. The device achieves plunger-and-barrier-gate gaps of approximately 6 nanometres between control electrodes. imec emphasized the manufacturing path: the device was produced on a 300mm CMOS-compatible line using ASML's High-NA EUV lithography system at imec's Leuven facility (a system class of which fewer than ten are installed worldwide as of 2026-Q2). imec's framing positions the demonstration as a fabrication-technology threshold enabling theoretical integration of 'millions of quantum bits' on a single chip, leveraging the company's prior work showing 'CMOS-compatible processes can lead to low charge noise and stable qubit operation.' The announcement does not report two-qubit gate fidelity, qubit-count benchmarks, T1/T2 coherence times, or specific lattice dimensionality; the milestone is fabrication-technology rather than qubit-performance-benchmark. Trade-press independent coverage at The Quantum Insider, SemiWiki, HPCwire, Digiconasia, New Electronics, and Embedded confirmed the world-first lithography-method-applied-to-quantum-dot-qubit framing and the 6nm gap dimension. imec did not disclose a customer-engagement pathway, an open-foundry quantum-dot-qubit programme, or a near-term spin-out commercialisation plan from this specific demonstration.
Score 7 ÔÇö anchor ┬º8.2 row 7 'Credible benchmark result with industry-wide implications' applied to a fabrication-technology threshold demonstration that addresses the principal long-standing constraint on silicon-spin-qubit scale-up: precision-patterning of sub-10nm inter-gate gaps at production-line reproducibility. Held at 7 rather than 8 because: (a) no qubit-performance benchmark (gate fidelity, coherence time, single-qubit or two-qubit error rate) is reported alongside the fabrication demonstration ÔÇö the milestone is a manufacturing-technology threshold, not an operating-qubit benchmark; (b) the 'millions of qubits' framing is theoretical-potential language rather than a demonstrated qubit-count; (c) no customer engagement, partner-foundry programme, or near-term commercialisation pathway was announced ÔÇö the demonstration is a research-and-development milestone from a national-research-institute rather than a product launch; (d) the High-NA EUV equipment base is concentrated (fewer than ten ASML EXE-class systems worldwide), and the demonstration's reproduction at other facilities depends on ASML system availability, which is the gating-factor for fab-to-fab portability. Held above 6 because: (a) High-NA EUV is the principal lithography-technology pathway to sub-10nm-gap silicon-spin-qubit arrays, and imec is the world-leading shared semiconductor R&D facility with the ASML EXE-class installed base ÔÇö the demonstration is a credible milestone, not a press-release breakthrough; (b) the result validates the 300mm-CMOS-compatible silicon-spin-qubit thesis that underpins multiple tracked entities (Diraq's silicon-CMOS spin-qubit programme ÔÇö recipient of the up-to-$38M 2026-05-21 CHIPS LOI; Quobly's CEA-Leti silicon-spin-qubit programme; SQC Australia; Intel's Tunnel Falls silicon-spin-qubit pipeline; CEA-Leti's broader silicon-spin work) ÔÇö providing fabrication validation for the architectural bet; (c) the 6nm gap dimension is at the lower edge of the silicon-spin-qubit-array design space and enables increased inter-qubit exchange coupling for fast two-qubit gates and high-density qubit packing; (d) the demonstration is at imec, the multi-national shared semiconductor R&D facility that historically accelerates fab-to-fab technology transfer (the SPINS quantum-foundry-line programme at imec is the analogous open-foundry vehicle), positioning the demonstration as a foundation for follow-on customer engagements; (e) the ASML High-NA EUV machine class anchors the demonstration to the most advanced commercial lithography technology, validating quantum-hardware fabrication on the same equipment used for advanced-node logic and memory. Source confidence high (imec primary press release on imec-int.com, PRNewswire distribution, multiple Tier-1 trade-press confirmations including SemiWiki, HPCwire, The Quantum Insider, Embedded, New Electronics, Digiconasia); interpretation confidence medium (the milestone is fabrication-technology rather than operating-qubit benchmark, so the qubit-performance implications cannot be quantified from this announcement alone ÔÇö qubit-count, gate fidelity, and coherence benchmarks will surface in follow-on publications or peer-reviewed preprints).
Watch for: (a) imec follow-on publications reporting qubit-performance benchmarks on the High-NA EUV-fabricated device ÔÇö gate fidelity, T1/T2 coherence, single-shot readout, two-qubit gate operation ÔÇö likely to appear at the IEDM December 2026 conference, VLSI Symposium June 2026, or via arXiv submission within 6-12 months; (b) Diraq engagement with the imec High-NA EUV pathway ÔÇö Diraq's silicon-CMOS spin-qubit programme, recipient of the up-to-$38M 2026-05-21 CHIPS LOI, is the most direct commercial beneficiary of this fabrication-technology validation; a Diraq-imec foundry-engagement announcement would be a score-7+ follow-on; (c) Quobly (CEA-Leti spin-out) and SQC Australia engagement with the imec High-NA EUV pathway, as both are silicon-spin-qubit-architecture commercial-entity peers; (d) Intel's response ÔÇö Intel's Hillsboro D1X superconducting-qubit process and Tunnel Falls 12-qubit silicon-spin-qubit pipeline are positioned for the same fabrication-technology threshold; the Intel-Diraq-vs-imec competitive dynamics for the silicon-spin-qubit fabrication ecosystem are the principal industry-structure question; (e) the impact on the IBM Anderon foundry positioning ÔÇö Anderon's announced scope is 'superconducting first, expand into other modalities later' (event 2026-05-21-ibm-anderon-quantum-foundry-1b-doc-1b-ibm-match); imec's High-NA EUV silicon-spin-qubit capability provides a non-Anderon production path for silicon-spin-qubit customers, potentially fragmenting the future Anderon customer cohort; (f) the impact on the GlobalFoundries Quantum Technology Solutions (QTS) positioning ÔÇö GFS's QTS business unit (event 2026-05-21-globalfoundries-quantum-technology-solutions-launch-375m-doc-loi) is positioned as a multi-modality foundry-service offering; the imec High-NA EUV result is a competitive reference point but not a direct competitor since imec is a shared R&D facility, not a foundry-services provider; (g) the response from non-EUV silicon-spin-qubit pathways (electron-beam lithography, multi-patterning DUV) ÔÇö researchers exploring those paths will face a credibility test against the High-NA EUV pathway; (h) ASML stock-price reaction ÔÇö the High-NA EUV system's qualification on a new device class (quantum-dot qubits) modestly expands the addressable market beyond logic-and-memory, supporting ASML's High-NA capex narrative; (i) Belgian / EU national-quantum-strategy positioning ÔÇö Belgium's federal quantum-strategy through Vlaams Initiatief voor Quantumcomputing (VIQ) and imec's institutional position will be reinforced by the world-first demonstration. Opens a new sub-thread 'High-NA EUV silicon-spin-qubit fabrication pathway' and strengthens the existing open threads 'Silicon-spin-qubit fault-tolerant-architecture commercialisation' (Diraq, Quobly, Intel Tunnel Falls, SQC) and 'imec SPINS quantum-foundry-line programme.'