IBM runs Relay-BP qLDPC error-correction decoder in real time on off-the-shelf AMD FPGAs
On 2025-10-24 IBM disclosed that its Relay-BP belief-propagation decoder for quantum low-density parity-check (qLDPC) codes ran in real time on a standard AMD VU19P field-programmable gate array (FPGA), completing decoding in under ~480 nanoseconds (within the ~1-microsecond budget required for real-time error correction) and reported a 5x-10x speedup over prior qLDPC decoders. IBM framed the result as removing the need for custom decoding silicon and as advancing its Starling fault-tolerant roadmap roughly a year ahead of schedule.
Demonstrating real-time qLDPC decoding on commodity classical hardware is a meaningful, near-term-consequential engineering result for the fault-tolerance roadmap, lowering a key cost-and-complexity barrier to scalable error correction.
If decoding can ride on off-the-shelf FPGAs, the classical-control bill of materials for fault-tolerant machines drops substantially, strengthening IBM's Starling timeline and pressuring rivals reliant on bespoke decoders; it also deepens the IBM-AMD hybrid-computing alliance.